Yulei Wu
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Abstract
The traffic pattern has significant impact on the performance of network-on-chip. Many recent studies have shown that multimedia applications can be supported in on-chip interconnects. Driven by the motivation of evaluating on-chip interconnects in multimedia embedded systems, a new analytical model is proposed to investigate the performance of the fat-tree based on-chip interconnection network under bursty multimedia traffic and nonuniform message destinations. Extensive simulation experiments are conducted to validate the accuracy of the model, which is then adopted as a cost-efficient tool to investigate the effects of bursty multimedia traffic with nonuniform destinations on the network performance.
- Ascia, G., Catania, V., Palesi, M., and Patti, D. 2008. Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Trans. Comput. 57, 809--820. Google Scholar
Digital Library
- Benini, L. and Micheli, G. D. 2002. Networks on chip: A new SoC paradigm. IEEE Comput. 35, 70--78. Google ScholarDigital Library
- Bjerregaard, T. and Mahadevan, S. 2006. A survey of research and practices of network-on-chip. ACM Comput. Surv. 38, Article No. 1. Google ScholarDigital Library
- Dally, W. J. and Towles, B. 2001. Route packets, not wires: onchip interconnection networks. In Proceedings of the Design Automation Conference, 684--689. Google ScholarDigital Library
- Dally, W. J. and Towles, B. P. 2004. Principles and Practices of Interconnection Network. Morgan Kaufmann. Google ScholarDigital Library
- Duato, J., Yalamanchili, S., and Ni, L. 2003. Interconnection Networks: An Engineering Approach. Morgan Kaufmann. Google ScholarDigital Library
- Ferng, H.-W. and Chang, J.-F. 2001. Connection-wise end-to-end performance analysis of queuing networks with MMPP inputs. Perf. Eval. 43, 39--62. Google ScholarDigital Library
- Fischer, W. and Meier-Hellstern, K. 1993. The Markov-modulated poisson process (MMPP) cookbook. Perf. Eval. 18, 149--171. Google ScholarDigital Library
- Grecu, C., Pande, P. P., Ivanov, A., and Saleh, R. 2004. Structured interconnect architecture: A solution for the non-scalability of bus-based SoCs. In Proceedings of the 14th ACM Great Lakes Symposium on VLSI, 192--195. Google ScholarDigital Library
- Heffes, H. 1980. A class of data traffic processes-covariance function characterization and related queueing results. Bell Syst. Tech. J. 59, 897--929.Google ScholarCross Ref
- Heffes, H. and Lucantoni, D. M. 1986. A Markov modulated characterization of packetized voice and data traffic and related statistical multiplexer performance. IEEE J. Select. Areas Commun. 4, 856--867. Google ScholarDigital Library
- Javadi, B., Akbari, M. K., and Abawajy, J. H. 2006. A performance model for analysis of heterogeneous multi-cluster systems. Parall. Comput. 32, 831--851. Google ScholarDigital Library
- Kapre, N., Mehta, N., Delorimier, M., Rubin, R., Barnor, H., Wilson, M. J., Wrighton, M., and Dehon, A. 2006. Packet switched vs. time multiplexed FPGA overlay networks. In Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), 205--216. Google ScholarDigital Library
- Kleinrock, L. 1975. Queueing Systems. John Wiley, New York. Google ScholarDigital Library
- Kodi, A. K., Sarathy, A., and Louri, A. 2008. Adaptive channel buffers in on-chip interconnection networks: A power and performance analysis. IEEE Trans. Comput. 57, 1169--1181. Google ScholarDigital Library
- Lee, H. G., Ogras, U. Y., Marculescu, R., and Chang, N. 2006. Design space exploration and prototyping for on-chip multimedia applications. In Proceedings of the 43rd ACM/IEEE Design Automation Conference (DAC'06), 137--142. Google ScholarDigital Library
- Lin, X.-Y., Chung, Y.-C., and Huang, T.-Y. 2004. A multiple LID routing scheme for fat-tree-based Infiniband networks. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS'04), CD-ROM.Google Scholar
- Liu, K.-H., Ling, X., Shen, X., and Mark, J. W. 2008. Performance analysis of prioritized MAC in UWB WPAN with bursty multimedia traffic. IEEE Trans. Vehic. Tech. 57, 2462--2473.Google ScholarCross Ref
- Majeti, D., Pasalapudi, A., and Yalamanchili, K. 2009. Low energy tree based network on chip architectures using homogeneous routers for bandwidth and latency constrained multimedia applications. In Proceedings of the International Conference on Emerging Trends in Engineering and Technology (ICETET'09), 358--363. Google ScholarDigital Library
- Marculescu, R., Ogras, U. Y., Peh, L.-S., Jerger, N. E., and Hoskote, Y. 2009. Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans. Comput. Aided Desi. Integ. Circ. Syst. 28, 3--21. Google ScholarDigital Library
- Matsutani, H., Koibuchi, M., Yamada, Y., Hsu, D. F., and Amano, H. 2009. Fat H-tree: A cost-efficient tree-based on-chip network. IEEE Trans. Paral. Distrib. Syst. 20, 1126--1141. Google ScholarDigital Library
- Meier-Hellstern, K. S. 1989. The Analysis of a queue arising in overflow models. IEEE Trans. Commun. 37, 367--372.Google ScholarCross Ref
- Min, G. and Ould-Khaoua, M. 2004. Performance modelling and evaluation of virtual channels in multicomputer networks with bursty traffic. Perf. Eval. 58, 143--162. Google ScholarDigital Library
- Mirza-Aghatabar, M., Koohi, S., Hessabi, S., and Pedram, M. 2007. An empirical investigation of mesh and torus NoC topologies under different routing algorithms and traffic models. In Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD'07), 19--26. Google ScholarDigital Library
- Moadeli, M., Shahrabi, A., Vanderbauwhede, W., and Maji, P. 2010. An analytical performance model for the spidergon NoC with virtual channels. J. Syst. Archit. 56, 16--26. Google ScholarDigital Library
- Ogras, U. Y. and Marculescu, R. 2008. Analysis and optimization of prediction-based flow control in networks-on-chip. ACM Trans. Des. Automat. Electron. Syst. 13, Article No. 11. Google ScholarDigital Library
- Ould-Khaoua, M. and Sarbazi-Azad, H. 2001. An analytical model of adaptive wormhole routing in hypercubes in the presence of hot spot traffic. IEEE Trans. Paral. Distrib. Syst. 12, 283--292. Google ScholarDigital Library
- Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54, 1025--1040. Google ScholarDigital Library
- Peng, H.-K. and Lin, Y.-L. 2010. An optimal warning-zone-length assignment algorithm for real-time and multiple-qos on-chip bus arbitration. ACM Trans. Embed. Comput. Syst. 9, Article No. 35. Google ScholarDigital Library
- Pfister, G. J. and Norton, V. A. 1985. Hot-spot contention and combining in multistage interconnection networks. IEEE Trans. Comput. 34, 943--948.Google ScholarCross Ref
- Salminen, E., Kulmala, A., and Hamalainen, T. D. 2008. Survey of network-on-chip proposals. White Paper, OCP-IP.Google Scholar
- Sanchez, D., Michelogiannakis, G., and Kozyrakis, C. 2010. An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Trans. Architect. Code Optim. 7, Article No. 4. Google ScholarDigital Library
- Sarbazi-Azad, H., Ould-Khaoua, M., and Mackenzie, L. M. 2001. Analytical modeling of wormhole-routed k-ary n-cubes in the presence of hot-spot traffic. IEEE Trans. Comput. 50, 623--634. Google ScholarDigital Library
- Schroeder, M. D., Birrell, A. D., Burrows, M., Murray, H., Needham, R. M., Rodeheffer, T. L., Satterthwaite, E. H., and Thacker, C. P. 1991. Autonet: A high-speed, self-configuring local area network using point-to-point links. IEEE J. Select. Areas Commun. 9, 1318--1335. Google ScholarDigital Library
- Shah-Heydari, S. and Le-Ngoc, T. 2000. MMPP models for multimedia traffic. Telecommun. Syst. 15, 273--293.Google ScholarDigital Library
- Taktak, S., Desbarbieux, J.-L., and Encrenaz, E. 2008. A tool for automatic detection of deadlock in wormhole networks on chip. ACM Trans. Desi. Automat. Electron. Syst. 13, Article No. 6. Google ScholarDigital Library
- Varatkar, G. and Marculescu, R. 2002. Traffic analysis for on-chip networks design of multimedia applications. In Proceedings of the 39th Annual Design Automation Conference (DAC'02), 795--800. Google ScholarDigital Library
- Varatkar, G. and Marculescu, R. 2004. On-chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Trans. Very Large Scale Integ. (VLSI) Syst. 12, 108--119. Google ScholarDigital Library
- Wang, Z., Xu, J., Wu, X., Ye, Y., Zhang, W., Liu, W., Nikdast, M., Wang, X., and Wang, Z. 2012. A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip. In Proceedings of the 2012 IEEE Optical Interconnects Conference, 100--101.Google Scholar
- Wu, Y., Min, G., Ould-Khaoua, M., and Yin, H. 2008. Analytical modeling of pipelined circuit switching with bursty and hot-spot traffic. In Proceedings of the the 10th IEEE International Conference on High Performance Computing and Communications (HPCC'08). IEEE Computer Society, Washington, DC, USA, 470--477. Google ScholarDigital Library
- Wu, Y., Min, G., Ould-Khaoua, M., and Yin, H. 2011. Modelling and analysis of pipelined circuit switching in interconnection networks with bursty traffic and hot-spot destinations. J. Sys. Softw. 84, 2097--2106. Google ScholarDigital Library
- Xiong, Y., Liu, S., and Sun, P. 2001. On the defense of the distributed denial of service attacks: An on-off feedback control approach. IEEE Trans. Syst. Man Cybernet. - Part A: Syst. Humans. 31, 282--293. Google ScholarDigital Library
- Zhang, Y. and Jones, A. K. 2009. Non-uniform fat-meshes for chip multiprocessors. In Proceedings of the IEEE International Symposium on Parallel and Distributed Processing (IPDPS'09), 1--8. Google ScholarDigital Library
Index Terms
- An analytical model for on-chip interconnects in multimedia embedded systems
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